Semiconductors devices are increasingly being scaled down and gate dielectrics become thinner. At such a small dimension, any tunneling through a gate dielectric layer to the underlying channel region significantly increases gate-to-channel leakage current and increases power consumption. Gate dielectrics are therefore required to have high density and fewer pores.
High-k materials are commonly used as gate dielectrics for MOSFET devices. However, high-k materials have the disadvantage that their densities are lower than conventional thermally grown, low-k silicon dioxide. One of the methods of improving density is annealing, by which the material density is increased and thus electrical properties are improved.
Some conventional methods of gate-dielectric annealing are performed by rapid thermal annealing (RTA) or furnace annealing, which requires temperature as high as around 700° C. Since wafers are typically kept at high temperature for a long period, conventional rapid thermal annealing and furnace annealing have drawbacks of agglomeration formation, high thermal budget cost, and high diffusion of impurities.
Laser spike annealing (LSA) has been developed to overcome the shortfalls of RTA. Conventional methods of LSA involve arc scanning in which the laser is scanned in an arc across the semiconductor wafer. For example, FIGS. 1A and 1B illustrate a conventional LSA arc-scanning process of a semiconductor wafer 100. As shown in FIG. 1A, a semiconductor wafer 100 is placed on a pedestal 102 which may move as indicated by the arrows. A laser source 104 directs a beam of light 106 onto the semiconductor wafer 100 at an angle θ from an axis normal to the plane of the semiconductor wafer 100. FIG. 1B illustrates the conventional scanning paths 108a-108g of the laser beam 106 across the surface of the semiconductor wafer 100. In a conventional arc-scanning process, the laser beam 106 will scan path 108a first followed by 108b and so on until the final inverted “fill-in” scan 108g is performed.
While these conventional methods of LSA arc-scanning overcome some of the disadvantages of RTA, a semiconductor wafer 100 may have large variations in material characteristics that are difficult to account for using the conventional LSA methodology. The material variations may extend from one die to another which may negatively affect the performance of the integrated circuits formed on the dies and wafer 100.
Accordingly, an improved method of laser annealing for semiconductor wafers is desirable.